LTC3220/-1 Datasheet by Analog Devices Inc.

l , LI” LTC322O LTC3220-1 TECHNOLOGY W M YHFMF —> —L— L7HEWEAR 1
LTC3220/LTC3220-1
1
32201fd
For more information www.linear.com/LTC3220
Typical applicaTion
FeaTures
applicaTions
DescripTion
360mA Universal
18-Channel LED Driver
The LT C
®
3220/LTC3220-1 are highly integrated multi-
display LED drivers. These parts contain a high efficiency,
low noise charge pump to provide power to up to eighteen
universal LED current sources. The LTC3220/LTC3220-1
require only five small ceramic capacitors to form a
complete LED power supply and current controller.
The LED currents are set by an internal precision current
reference. Independent dimming, on/off, blinking and
gradation control for all universal current sources are
achieved via the I2C serial interface. 6-bit linear DACs are
available to adjust brightness levels independently for each
universal LED current source.
The LTC3220/LTC3220-1 charge pump optimizes efficiency
based on the voltage across the LED current sources. The
part powers up in 1x mode and will automatically switch
to boost mode whenever any enabled LED current source
begins to enter dropout. The first dropout switches the
parts into 1.5x mode and a subsequent dropout switches
the LTC3220/LTC3220-1 into 2x mode. The parts reset to
1x mode whenever a data bit is updated via the I2C port.
n Eighteen 20mA Universal Current Sources with
64-Step Linear Brightness Control
n Independent On/Off, Brightness Level, Blinking and
Gradation Control for Each Current Source Using
2-Wire I2C Interface
n Low Noise Multi-Mode Charge Pump (1x, 1.5x, 2x)
Provides Up to 91% Efficiency
n Slew Limited Switching Reduces Conducted and
Radiated Noise (EMI)
n Up to 360mA Total Output Current
n Internal Current Reference
n Single Reset Pin for Asynchronous Shutdown and
Reset of All Data Registers
n Two I2C Addresses Are Available (LTC3220: 0011100,
LTC3220-1: 0011101)
n Automatic or Forced Mode Switching
n Internal Soft-Start Limits Inrush Current
n Short-Circuit/Thermal Protection
n 4mm × 4mm Ultrathin (0.55mm) 28-Lead QFN
Package
n Video Phones with QVGA+ Displays
n Keypad Lighting
n General/Miscellaneous Lighting
L, LT , LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6411531.
DVCC
I2C
RESET
0.1µF
C1P
VIN
DVCC
SCL/SDA
VIN C1
2.2µF
C2
2.2µF
C3
2.2µF
CPO
ULED1-18
C1M
GND
C2P
LTC3220
LTC3220-1
C2M
C4
4.7µF
RGB1
3220 TA01
18
RST
RGB2 RGB3 RGB4 MAIN
6-LED Main, 4 RGB LEDs
LTC3220/LTC3220—1
LTC3220/LTC3220-1
2
32201fd
For more information www.linear.com/LTC3220
pin conFiguraTionabsoluTe MaxiMuM raTings
VIN, DVCC, CPO to GND ................................ –0.3V to 6V
ULED1-ULED18 to GND ................................ –0.3V to 6V
SDA, SCL, RST ........................... –0.3V to (DVCC + 0.3V)
ICPO (Continuous) (Note 2) .................................. 360mA
IULED1-18 (Note 2) ...................................................25mA
CPO Short-Circuit Duration .............................. Indefinite
Operating Temperature Range (Note 3)
LTC3220E/LTC3220E-1 ........................–40°C to 85°C
LTC3220I/LTC3220I-1 ........................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 4)
28 27 26 25 24 23
8 9
TOP VIEW
29
PF PACKAGE
28-LEAD UTQFN (4mm × 4mm)
10 11 12 13 14
ULED1
ULED2
ULED3
ULED4
ULED5
ULED6
ULED7
ULED18
ULED17
ULED16
ULED15
ULED14
ULED13
ULED12
CPO
C1P
C2P
RST
VIN
C1M
C2M
ULED8
ULED9
DVCC
SCL
SDA
ULED10
ULED11
16
15
17
18
19
20
21
6
7
5
4
3
2
1
22
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3220EPF#PBF LTC3220EPF#TRPBF 3220T 28-Lead UTQFN (4mm × 4mm) –40°C to 85°C
LTC3220EPF-1#PBF LTC3220EPF-1#TRPBF 2201T 28-Lead UTQFN (4mm × 4mm) –40°C to 85°C
LTC3220IPF#PBF LTC3220IPF#TRPBF 3220T 28-Lead UTQFN (4mm × 4mm) –40°C to 125°C
LTC3220IPF-1#PBF LTC3220IPF-1#TRPBF 2201T 28-Lead UTQFN (4mm × 4mm) –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage l2.9 5.5 V
IVIN Operating Current ICPO = 0, 1x Mode
ICPO = 0, 1.5x Mode
ICPO = 0, 2x Mode
580
2.4
3.2
µA
mA
mA
DVCC UVLO Threshold 1 V
DVCC Operating Voltage l1.5 5.5 V
VIN UVLO Threshold 1.5 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2µF, C4 = 4.7µF,
unless otherwise noted.
LTC3220/LTC3220—1
LTC3220/LTC3220-1
3
32201fd
For more information www.linear.com/LTC3220
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2µF, C4 = 4.7µF,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Shutdown Current l3.2 7 µA
DVCC Shutdown Current l1 µA
Universal LED Current, 6-Bit Linear DACs, ULED = 1V
Full-Scale LED Current l18 20 22 mA
Minimum (ILSB) LED Current Step 0.314 mA
Minimum Programmable Current ULED Data Register Programmed to
0b00000001
0.395 mA
LED Current Matching Any Two Outputs, 50% of FS 1.5 %
LED Dropout Voltage ILED = FS 120 mV
Blink Rate Period REG19, D4 = 0
REG19, D4 = 1
1.25
2.5
Sec
Sec
ULED Up/Down Gradation Ramp Times REG19, D1 = 1, D2 = 0
REG19, D1 = 0, D2 = 1
REG19, D1 = 1, D2 = 1
0.24
0.48
0.96
Sec
Sec
Sec
Gradation Period REG19, D1 = 1, D2 = 0
REG19, D1 = 0, D2 = 1
REG19, D1 = 1, D2 = 1
0.313
0.625
1.25
0.410
0.820
1.640
Sec
Sec
Sec
VOL General Purpose Output Mode (GPO) IOUT = 1mA, Single Output Enabled 5 mV
LED Turn-On Delay From Stop Bit, Part Enabled 4 µs
Charge Pump (CPO)
1x Mode Output Impedance 0.6 Ω
1.5x Mode Output Impedance VIN = 3V, VCPO = 4.2V (Note 5) 3.6 Ω
2x Mode Output Impedance VIN = 3V, VCPO = 4.8V (Note 5) 4.1 Ω
CPO Regulation Voltage 1.5x Mode, ICPO = 20mA
2x Mode, ICPO = 20mA
4.5
5.03
V
V
Clock Frequency l0.65 0.85 1.05 MHz
CPO Short-Circuit Detection
Threshold Voltage l0.4 1.3 V
Test Current CPO = 0V l10 30 mA
SDA, SCL, RST
VIL l0.3 • DVCC V
VIH l0.7 • DVCC V
IIH SDA, SCL, RST = DVCC l–1 1 µA
IIL SDA, SCL, RST = 0V l–1 1 µA
VOL Digital Output Low (SDA) IPULLUP = 3mA l0.12 0.4 V
RST Timing Reset Pulse Duration 20 ns
Serial Port Timing (Notes 6, 7)
fSCL Clock Operating Frequency 400 kHz
tBUF Bus Free Time Between Stop and Start
Condition
1.3 µs
tHD,STA Hold Time After (Repeated) Start Condition 0.6 µs
tSU,STA Repeated Start Condition Setup Time 0.6 µs
tSU,STO Stop Condition Setup Time 0.6 µs
LTC3220/LT03220—1
LTC3220/LTC3220-1
4
32201fd
For more information www.linear.com/LTC3220
Typical perForMance characTerisTics
Mode Switch Dropout Times 1.5x Mode CPO Ripple 2x Mode CPO Ripple
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Based on long term current density limitations.
Note 3: The LTC3220E/LTC3220E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3220I/LTC3220I-1
are guaranteed to meet performance specifications over the full –40°C to
125°C operating temperature range.
TA = 25°C unless otherwise noted.
Note 4: These devices include overtemperature protection that is intended
to protect the devices during momentary overload conditions. Junction
temperatures will exceed 125°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may result in device degradation or failure.
Note 5: 1.5x mode output impedance is defined as (1.5VIN – VCPO)/IOUT.
2x mode output impedance is defined as (2VIN – VCPO)/IOUT.
Note 6: All values are referenced to VIH and VIL levels.
Note 7: Guaranteed by design.
VCPO
1V/DIV
VIN = 3.6V 250µs/DIV 3220 G01
1×
1.5×
2×
VCPO
20mV/DIV
AC COUPLED
VIN = 3.6V
ICPO = 200mA
CCPO = 4.7µF
500ns/DIV 3220 G02
VCPO
20mV/DIV
AC COUPLED
VIN = 3.6V
ICPO = 200mA
CCPO = 4.7µF
500ns/DIV 3220 G03
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2µF, C4 = 4.7µF,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tHD,DAT(OUT) Data Hold Time 0 900 ns
tHD,DAT(IN) Input Data Hold Time 0 ns
tSU,DAT Data Setup Time 100 ns
tLOW Clock Low Period 1.3 µs
tHIGH Clock High Period 0.6 µs
tfClock Data Fall Time 20 300 ns
trClock Data Rise Time 20 300 ns
tSP Spike Suppression Time 50 ns
LTC3220/LTC3220—1 zwzsucl TA: 25% \\ L7 LJUW 5
LTC3220/LTC3220-1
5
32201fd
For more information www.linear.com/LTC3220
1x Mode Switch Resistance
vs Temperature
1.5x Mode Charge Pump Open-Loop
Output Resistance vs Temperature 1.5x Mode CPO Voltage vs ICPO
2x Mode Charge Pump Open-Loop
Output Resistance vs Temperature 2x Mode CPO Voltage vs ICPO
Oscillator Frequency
vs VIN Voltage
VIN Shutdown Current
vs VIN Voltage DVCC Current vs DVCC Voltage
Typical perForMance characTerisTics
TA = 25°C unless otherwise noted.
TEMPERATURE (°C)
–40
SWITCH RESISTANCE (Ω)
0.45
0.50
0.55
5125
3220 G04
0.40
0.35
0.30 –25 –10 20 35 50 65 80 95 110
0.60
0.65
0.70
0.75
0.80
VIN = 3.3V
VIN = 3.9V
VIN = 3.6V
TEMPERATURE (°C)
–40
2.5
OPEN-LOOP OUTPUT RESISTANCE (Ω)
2.7
2.9
3.1
3.3
3.5
3.9
4.1
4.3
4.5
–25 –10 5 6520 35 50 80 95 110
3220 G05
125
ICPO (mA)
0
3.6
CPO VOLTAGE (V)
3.8
4.0
4.2
4.4
4.8
3V
3.1V
3.3V
3.4V
3.6V
60 120 180 240
3220 G06
300 360
4.6
3.2V
3.5V
TEMPERATURE (°C)
–40
3.9
4.1
4.3
4.5
4.7
4.9
95
3220 G07
3.7
3.5
–25 –10 35205 50 65 80 110 125
3.3
3.1
2.9
OPEN-LOOP OUTPUT RESISTANCE (Ω)
ICPO (mA)
0
4.2
CPO VOLTAGE (V)
4.4
4.6
4.8
60 120 180 240
3220 G08
300
5.0
5.2
4.3
4.5
4.7 3V
4.9
5.1
360
3.1V
3.2V
3.3V-3.6V
VIN VOLTAGE (V)
2.9
FREQUENCY (kHz)
770
780
790
5.5
3220 G09
760
750
730 3.55 4.2 4.85
740
810
TA = 25°C
TA = 125°C
TA = –45°C
TA = 85°C
800
VOLTAGE (V)
2.9
1.5
VIN SHUTDOWN CURRENT (µA)
2.5
3.5
4.5
5.5
6.5
7.5
3.55 4.2 4.85 5.5
3220 G10
TA = 25°C
TA = 125°C
TA = 85°C
TA = –40°C
1x Mode No Load VIN Current
vs VIN Voltage
DVCC VOLTAGE (V)
1.5
0
DVCC CURRENT (µA)
0.5
1.0
1.5
2.0
2.5
3.0
2.5 3.5 4.5 5.5
3220 G11
RST = SDA = DVCC
fSCL = 400kHz
fSCL = 10kHz
fSCL = 100kHz
VIN VOLTAGE (V)
2.9
580
VIN CURRENT (µA)
585
590
595
600
605
610
3.55 4.2 4.85 5.5
3220 G12
LTC3220/LTC3220—1 6 L7LJ1‘JW
LTC3220/LTC3220-1
6
32201fd
For more information www.linear.com/LTC3220
pin FuncTions
Typical perForMance characTerisTics
TA = 25°C unless otherwise noted.
18-LED ULED Display Efficiency
vs VIN Voltage
ULED1-ULED18 (Pins 1-9,13-21): Current Source Outputs
for Driving LEDs. The LED current can be set from 0mA to
20mA in 64 steps via software control and internal 6-bit
linear DAC. Each output can be disabled by setting the
associated data register REG1 to REG18 low. ULED1 to
ULED18 can also be used as I2C controlled open-drain gen-
eral purpose outputs. Connect unused outputs to ground.
DVCC (Pin 10): Supply Voltage for All digital I/O lines.
This pin sets the logic reference level of the LTC3220/
LTC3220-1. DVCC will reset the data registers when set
below the undervoltage lockout threshold. A 0.1µF X5R
or X7R ceramic capacitor should be connected to ground.
SCL (Pin 11): I2C Clock Input. The logic level for SCL is
referenced to DVCC.
ULED Current vs Input Code
INPUT CODE (HEX)
0 09
0
ULED CURRENT (mA)
10
25
12 24 2D
3220 G16
5
20
15
1B 36 3F
VIN VOLTAGE (V)
2.9
ULED EFFICIENCY (PLED/PIN) (%)
100
10
90
70
50
30
80
60
40
20
04.5253.875 5.175
3220 G17
5.54.23.55 4.853.225
1.5x Mode VIN Current vs ICPO
(IVIN – 1.5ICPO)
2x Mode VIN Current vs ICPO
(IVIN – 2ICPO)
ULED Pin Current
vs ULED Pin Voltage
ICPO (mA)
0
V
IN
CURRENT (mA)
6
8
10
180 300
3220 G13
4
2
060 120 240
12
14
16
360
ICPO (mA)
0
14
12
10
8
6
4
2
0180 300
3220 G14
60 120 240 360
V
IN
CURRENT (mA)
ULED PIN VOLTAGE (V)
0
ULED PIN CURRENT (mA)
10
15
0.2
3220 G15
5
00.05 0.1 0.15
25
20
LTC3220/LTC3220—1
LTC3220/LTC3220-1
7
32201fd
For more information www.linear.com/LTC3220
pin FuncTions
–
+
24
1.22V
VIN
25 RST
10 DVCC
12 SDA
11 SCL
2223 2627
28
C2MC1M C2PC1P
CPO
29
EXPOSED
PAD
1
2
850kHz
OSCILLATOR
CONTROL
LOGIC
MASTER/SLAVE
REG
SHIFT REGISTER
CHARGE PUMP
18 UNIVERSAL
CURRENT SOURCES
AND DACS
3
4
5
6
7
18
8
9
ULED1
ULED2
ULED3
ULED4
ULED5
ULED6
ULED7
ULED8
ULED9
13
ULED10
14
ULED11
15
ULED12
16
ULED13
17
ULED14
18
ULED15
19
ULED16
20
ULED17
21
ULED18
3220 BD
block DiagraM
SDA (Pin 12): Input Data for the Serial Port. Serial data is
shifted in one bit per clock cycle to control the LTC3220/
LTC3220-1. The logic level is referenced to DVCC.
C1P, C2P, C1M, C2M (Pins 27, 26, 23, 22): Charge Pump
Flying Capacitor Pins. A 2.2µF X7R or X5R ceramic capacitor
should be connected from C1P to C1M and C2P to C2M.
VIN (Pin 24): Supply Voltage for the Entire Device. This pin
must be bypassed with a single 2.2µF low ESR ceramic
capacitor.
RST (Pin 25): Active Low Reset Input. RST Resets all
internal registers and forces LTC3220/LTC3220-1 into
shutdown mode.
CPO (Pin 28): Output of the Charge Pump. Used to power
all LEDs. A 4.7µF X5R or X7R ceramic capacitor should
be connected to ground.
Exposed Pad (Pin 29): Ground. The Exposed Pad must
be soldered to PCB ground.
LTC3220/LTC3220—1 8 L7LJ1‘JW
LTC3220/LTC3220-1
8
32201fd
For more information www.linear.com/LTC3220
operaTion
Power Management
The LTC3220/LTC3220-1 use a switched capacitor charge
pump to boost CPO as much as 2 times the input voltage
up to 5.1V. The part starts up in 1x mode. In this mode,
VIN is connected directly to CPO. This mode provides
maximum efficiency and minimum noise. The LTC3220/
LTC3220-1 will remain in 1x mode until an LED current
source drops out. Dropout occurs when a current source
voltage becomes too low for the programmed current
to be supplied. When dropout is detected, the LTC3220/
LTC3220-1 will switch into 1.5x mode. The CPO voltage
will then start to increase and will attempt to reach 1.5×
VIN up to 4.6V. Any subsequent dropout will cause the
part to enter the 2x mode. The CPO voltage will attempt
to reach 2× VIN up to 5.1V.
A 2-phase non-overlapping clock activates the charge
pump switches. In the 2x mode the flying capacitors are
charged on alternate clock phases from VIN to minimize
CPO voltage ripple. In 1.5x mode the flying capacitors are
charged in series during the first clock phase and stacked
in parallel on VIN during the second phase. This sequence
of charging and discharging the flying capacitors continues
at a constant frequency of 850kHz.
The current delivered by each LED current source is con-
trolled by an associated DAC. Each DAC is programmed
via the I2C port.
+
–
ROL
CPO
3220 F01
1.5VIN OR
2VIN
+
–
Figure 1. Charge Pump Open-Loop Thevenin Equivalent Circuit
Soft-Start
Initially, when the part is in shutdown, a weak switch
connects VIN to CPO. This allows VIN to slowly charge the
CPO output capacitor and prevent large charging currents
from occurring.
The LTC3220/LTC3220-1 also employ a soft-start feature
on the charge pump to prevent excessive inrush current
and supply droop when switching into the step-up modes.
The current available to the CPO pin is increased linearly
over a typical period of 125µs. Soft-start occurs at the
start of both 1.5x and 2x mode changes.
Charge Pump Strength
When the LTC3220/LTC3220-1 operate in either 1.5x mode
or 2x mode, the charge pump can be modeled as a Theve-
nin-equivalent circuit to determine the amount of current
available from the effective input voltage and effective
open-loop output resistance, ROL (Figure 1).
ROL is dependent on a number of factors including the
switching term, 1/(2fOSC • CF LY ), internal switch resis-
tances and the non-overlap period of the switching circuit.
However, for a given ROL, the amount of current available
will be directly proportional to the advantage voltage of
1.5VIN – CPO for 1.5x mode and 2VIN – CPO for 2x mode.
Consider the example of driving LEDs from a 3.1V supply.
LTC3220/LTC3220—1 VW VC PO 0L VW VCPO 0L L7 LJUW 9
LTC3220/LTC3220-1
9
32201fd
For more information www.linear.com/LTC3220
operaTion
If the LED forward voltage is 3.8V and the current sources
require 100mV, the advantage voltage for 1.5x mode is
3.1V • 1.5 – 3.8V – 0.1V or 750mV. Notice that if the input
voltage is raised to 3.2V, the advantage voltage jumps to
900mV, a 20% improvement in available strength.
From Figure 1, for 1.5x mode the available current is
given by:
OUT =1.5VIN −VCPO
R
(1)
For 2x mode, the available current is given by:
I
OUT =2VIN −VCPO
R
OL
(2)
Notice that the advantage voltage in this case is 3.1V •
2 – 3.8V – 0.1V = 2.3V. ROL is higher in 2x mode but a
significant overall increase in available current is achieved.
Mode Switching
The LTC3220/LTC3220-1 will automatically switch from
1x mode to 1.5x mode and subsequently to 2x mode
whenever a dropout condition is detected at an LED pin.
Dropout occurs when a current source voltage becomes
too low for the programmed current to be supplied. The
mode change will not occur unless dropout exists for
approximately 400µs.
The mode will automatically switch back to 1x whenever
a register is updated via the I2C port, when gradation
completes ramping down and after each blink period.
The parts can be forced to operate in 1x, 1.5x or 2x mode
by writing the appropriate bits into REG0. This feature may
be used for operating loads powered by CPO.
Non-programmed current sources do not affect dropout.
Universal Current Sources (ULED1 to ULED18)
There are eighteen universal 20mA current sources. Each
current source has a 6-bit linear DAC for current control.
The output current range is 0mA to 20mA in 64 steps.
Each current source is disabled when an all zero data word
is written. The supply current for that source is reduced
to zero. Unused outputs should be connected to GND.
GPO Mode
ULED1 to ULED18 can be used as general purpose outputs
(GPO). Current sources in the GPO mode can be used as
I2C controlled open-drain drivers. A ULED output can be
selected to operate in GPO mode by programming both Bit 6
and Bit 7 of its data register (REG1 to REG18) to a logic
high. In the GPO mode, dropout detection is disabled and
output swings to ground will not cause mode switching.
The GPOs can be programmed to either act as a switch
(strong pull-down mode) in which the part will only con-
sume approximately 3µA of quiescent current, or they can
be programmed to have a regulated current of up to 20mA
(current limit mode), which would require several hundred
microamps of additional quiescent current.
When a ULED output is used in GPO mode during shut-
down, CPO should not be used as a power source since
the current available from the CPO pin would be limited
by the weak pull-up current source. This weak pull-up is
only meant to keep the output capacitor charged to VIN
during shutdown and is unable to supply large amounts
of current. CPO can, however, be used as a power source
when the part is enabled.
Conversely, when a ULED output is used in GPO strong
pull-down mode, a current limiting resistor should be used
in series with the ULED output so that the current does
not exceed the Absolute Maximum rated current.
LTC3220/LTC322O'1
LTC3220/LTC3220-1
10
32201fd
For more information www.linear.com/LTC3220
operaTion
Blinking
Each universal output (ULED1 to ULED18) can be set to
blink with an on time of 0.156 seconds, or 0.625 seconds
and a period of 1.25 seconds, or 2.5 seconds via the I2C
port. The blinking rate is selected via REG19 and ULED
outputs are selected via REG1 to REG18. Blinking and
gradation rates are independent. Please refer to Applica-
tion Note 115 for detailed information and examples on
programming blinking.
Gradation
Universal LED outputs ULED1 to ULED18 can be set to
have the current ramp up and down at 0.24 seconds, 0.48
seconds and 0.96 seconds rates via the I2C port. Each of
these outputs can have either blinking or gradation enabled.
The gradation time is set via REG19 and ULED outputs
are selected via REG1 to REG18. The ramp direction is
also controlled via REG19. Setting the up bit high causes
gradation to ramp up, setting this bit to a low causes
gradation to ramp down. Please refer to Application Note
115 for detailed information and examples on program-
ming gradation.
When gradation is disabled the LED output current remains
at the programmed value.
The charge pump mode is reset to 1x mode after gradation
completes ramping down.
Chip Reset (RST)
The RST pin is used to turn off the chip, including the
charge pump and all ULED outputs, and clear all registers
in the LTC3220/LTC3220-1. When RST is low, the part is in
shutdown and cannot be programmed through the I2C port.
Shutdown Current
Shutdown occurs when all the current source data bits
have been written to zero, when the shutdown bit in REG0
is written with a logic 1, when RST is pulled low, or when
DVCC is set below the undervoltage lockout voltage.
Although the LTC3220/LTC3220-1 are designed to have
very low shutdown current, they will draw about 3µA
from VIN when in shutdown. Internal logic ensures that
the LTC3220/LTC3220-1 are in shutdown when DVCC is
low. Note, however that all of the logic signals that are
referenced to DVCC (SCL, SDA and RST) will need to be
at DVCC or below (i.e., ground) to avoid violation of the
absolute maximum specifications on these pins.
EMI Reduction
The flying capacitor pins C1M, C1P, C2M and C2P have
controlled slew rates to reduce conducted and radiated
noise.
Serial Port
The microcontroller compatible I2C serial port provides
all of the command and control inputs for the LTC3220/
LTC3220-1. Data on the SDA input is loaded on the rising
edge of SCL. D7 is loaded first and D0 last. There are 20
data registers, one address register and one sub-address
register. Once all address bits have been clocked into the
address register, an acknowledge occurs. The sub-address
LTC3220/LTC3220—1 \\\\\\\\\\\\\\\\\\\\\\\\\\\ |:|:|:|:|:|:|:|:| L7 LJUW 1 1
LTC3220/LTC3220-1
11
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Figure 3. Timing Parameters
ACK
123
ADDRESS WR
456789123456789123456789
0 0 1 1 1 0 0 0
00111010
S7 S6 S5 S4 S3 S2 S1 S0 76543210ACK
STOPSTART
SDA
SCL
ACK
ADDRESS
LTC3220-1
LTC3220 WR
00111000 S7 S6 S5 S4 S3 S2 S1 S0 76543210
SUB-ADDRESS DATA BYTE
3220 FO2
Figure 2. Bit Assignments
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tSU, STA
tHD, STA tSU, STO
3220 F03
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
trtf
tSP
register is then written to, followed by the data register.
Each data register has a sub-address. After the data register
has been written a load pulse is created after the stop bit.
The load pulse transfers all of the data held in the data
registers to the DAC registers. The stop bit can be delayed
until all of the data master registers have been written.
At this point the LED current will be changed to the new
settings. The serial port uses static logic registers so there
is no minimum speed at which it can be operated.
I2C Interface
The LTC3220/LTC3220-1 communicate with a host (mas-
ter) using the standard I2C 2-wire interface. The Timing
Diagram (Figure 3) shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources, such as the LTC1694 SMBus
accelerator, are required on these lines.
The LTC3220/LTC3220-1 are receive-only (slave) devices.
There are two I2C addresses available. The LTC3220 I2C
address is 0011100 and the LTC3220-1 I2C address is
0011101. The I2C address is the only difference between
the LTC3220 and LTC3220-1.
Write Word Protocol Used By the LTC3220/LTC3220-1
1 7 1 1 8 1 8 1 1
S Slave Address Wr A
*Sub-Address
A Data Byte A P**
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the first 5 bits, D0, D1, D2, D3 and D4.
**Stop can be delayed until all of the data registers have been written.
operaTion
LTC3220/LTC3220—1 12
LTC3220/LTC3220-1
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operaTion
Sub-Address Byte
MSB LSB
7 6 5 4 3 2 1 0 Register Function
0 0 0 0 0 0 0 0 REG0 COMMAND
0 0 0 0 0 0 0 1 REG1 ULED1
0 0 0 0 0 0 1 0 REG2 ULED2
0 0 0 0 0 0 1 1 REG3 ULED3
0 0 0 0 0 1 0 0 REG4 ULED4
0 0 0 0 0 1 0 1 REG5 ULED5
0 0 0 0 0 1 1 0 REG6 ULED6
0 0 0 0 0 1 1 1 REG7 ULED7
0 0 0 0 1 0 0 0 REG8 ULED8
0 0 0 0 1 0 0 1 REG9 ULED9
0 0 0 0 1 0 1 0 REG10 ULED10
0 0 0 0 1 0 1 1 REG11 ULED11
0 0 0 0 1 1 0 0 REG12 ULED12
0 0 0 0 1 1 0 1 REG13 ULED13
0 0 0 0 1 1 1 0 REG14 ULED14
0 0 0 0 1 1 1 1 REG15 ULED15
0 0 0 1 0 0 0 0 REG16 ULED16
0 0 0 1 0 0 0 1 REG17 ULED17
0 0 0 1 0 0 1 0 REG18 ULED18
0 0 0 1 0 0 1 1 REG19 GRAD/
BLINK
Register Sub-Address = 0000
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
Unused Unused Unused Unused Shutdown Force2x Force1p5x Quick write
Quick write 0
1
Serial write to each register
Parallel write, REG1 data is written to all eighteen universal registers
Force1p5 1
0
Forces charge pump into 1.5x mode
Enables mode logic to control mode changes based on dropout signal
Force2x 1
0
Forces charge pump into 2x mode
Enables mode logic to control mode changes based on dropout signal
Force1x D1 (Force1p5x) = 1 Forces Charge Pump into 1x Mode
D2 (Force2x) = 1
Shutdown 1
0
Shuts down part while preserving data in registers
Normal operation
REG0, Command Byte.
LTC3220/LTC3220—1 13
LTC3220/LTC3220-1
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Blink Times and Period Gradation Ramp Times and Period
D4 (GB4) D3 (GB3) On Time Period D2 (GB2) D1 (GB1) Ramp Time Period
0
0
1
1
0
1
0
1
0.625s
0.156s
0.625s
0.156s
1.25s
1.25s
2.5s
2.5s
0
0
1
1
0
1
0
1
Disabled
0.24s
0.48s
0.96s
Disabled
0.313s
0.625s
1.25s
RE
G19, Gradation and Blinking
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
Unused Unused Unused GB4 GB3 GB2 GB1 Up
Sub-Address 00001 to 10010 per Sub-Address Table
Blink/Gradation/Dropout Enable LED Current Data
MSB LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Normal
Blink Enabled
Gradation Enabled
GPO Mode*
Strong Pull-Down Mode
Current Limited Mode
High Impedance/Off
*(Gradation/Blink/Dropout Off)
0
0
1
1
1
0
0
1
0
1
1
0
D5
D5
D5
0
D5
0
D4
D4
D4
0
D4
0
D3
D3
D3
0
D3
0
D2
D2
D2
0
D2
0
D1
D1
D1
0
D1
0
D0
D0
D0
0
D0
0
Data Bytes
REG1 to REG18, Universal LED 6-bit linear DAC data with
blink/gradation.
Up 0
1
Gradation counts down
Gradation counts up
operaTion
Bus Speed
The I2C port is designed to be operated at speeds up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I2C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
Start and Stop Conditions
A bus-master signals the beginning of a communication
to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
LTC3220/LTC3220—1 14
LTC3220/LTC3220-1
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Byte Format
Each byte sent to the LTC3220/LTC3220-1 must be 8 bits
long followed by an extra clock cycle for the acknowledge
bit to be returned by the LTC3220/LTC3220-1. The data
should be sent to the LTC3220/LTC3220-1 most significant
bit (MSB) first.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (active low)
generated by the slave (LTC3220/LTC3220-1) lets the mas-
ter know that the latest byte of information was received.
The acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains a stable low during the high period of
this clock pulse.
Slave Address
Each version of LTC3220/LTC3220-1 responds to a unique
address which has been factory programmed (Table 1).
The eighth bit of the address byte (R/W) must be 0 for the
LTC3220/LTC3220-1 to recognize the address since it is a
write only device. This effectively forces the address to be
8 bits long where the least significant bit of the address
is 0. If the correct seven bit address is given but the R/W
bit is 1, the LTC3220/LTC3220-1 will not respond.
Table 1. LTC3220/LTC3220-1 Factory Programmed Slave
Address
PART NUMBER SLAVE ADDRESS
LTC3220 0011100
LTC3220-1 0011101
Bus Write Operation
The master initiates communication with the LTC3220/
LTC3220-1 with a START condition and a 7-bit address
followed by the write bit R/W = 0. If the address matches
that of the LTC3220/LTC3220-1, the LTC3220/LTC3220-1
return an acknowledge. The master should then deliver the
most significant sub-address byte for the data register to
operaTion
be written. Again the LTC3220/LTC3220-1 acknowledge
and then the data is delivered starting with the most sig-
nificant bit. This cycle is repeated until all of the required
data registers have been written. Any number of data
latches can be written. Each data byte is transferred to an
internal holding latch upon the return of an acknowledge.
After all data bytes have been transferred to the LTC3220/
LTC3220-1, the master may terminate the communication
with a STOP condition. Alternatively, a Repeat-START
condition can be initiated by the master and another chip
on theI2C bus can be addressed. This cycle can continue
indefinitely and the LTC3220/LTC3220-1 will remember the
last input of valid data that it received. Once all chips on
the bus have been addressed and sent valid data, a global
STOP condition can be sent and the LTC3220/LTC3220-1
will update all registers with the data that it had received.
In certain circumstances the data on the I2C bus may be-
come corrupted. In these cases the LTC3220/LTC3220-1
respond appropriately by preserving only the last set of
complete data that it has received. For example, assume
the LTC3220/LTC3220-1 has been successfully addressed
and is receiving data when a STOP condition mistakenly
occurs. The LTC3220/LTC3220-1 will ignore this STOP
condition and will not respond until a new START con-
dition, correct address, sub-address and new set of data
and STOP condition are transmitted.
Likewise, if the LTC3220/LTC3220-1 were previously ad-
dressed and sent valid data but not updated with a STOP,
they will respond to any STOP that appears on the bus
with only one exception, independent of the number of
Repeat-START’s that have occurred. If a Repeat-START is
given and the LTC3220/LTC3220-1 successfully acknowl-
edge their addresses and first byte, they will not respond to
a STOP until all bytes of the new data have been received
and acknowledged.
Quick Write
Registers REG1 to REG18 can be written in parallel by
setting Bit 0 of REG 0 high. When this bit is set high the
next write sequence to REG1 will write the data to REG1
through REG18, which are all of the universal LED registers.
IOUT L7 LJUW fOSC CCPO “£53 LTC3220/LTC3220—1 15
LTC3220/LTC3220-1
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VIN, CPO Capacitor Selection
The style and value of the capacitors used with the LTC3220/
LTC3220-1 determine several important parameters such
as regulator control loop stability, output ripple, charge
pump strength and minimum start-up time.
To reduce noise and ripple, it is recommended that low
equivalent series resistance (ESR) ceramic capacitors are
used for both CVIN and CCPO. Tantalum and aluminum
capacitors are not recommended due to high ESR.
The value of CCPO directly controls the amount of output
ripple for a given load current. Increasing the size of CCPO
will reduce output ripple at the expense of higher start-up
current. The peak-to-peak output ripple of the 1.5x mode
is approximately given by the expression:
VRIPPLEP-P =IOUT
3f
OSC
•C
CPO
(3)
where fOSC is the LTC3220/LTC3220-1 oscillator frequen-
cy or typically 850kHz and CCPO is the output storage
capacitor.
The output ripple in 2x mode is very small due to the fact
that load current is supplied on both cycles of the clock.
Both type and value of the output capacitor can significantly
affect the stability of the LTC3220/LTC3220-1. As shown
in the Block Diagram, the LTC3220/LTC3220-1 use a
control loop to adjust the strength of the charge pump to
match the required output current. The error signal of the
loop is stored directly on the output capacitor. The output
capacitor also serves as the dominant pole for the control
loop. To prevent ringing or instability, it is important for the
output capacitor to maintain at least 3.2µF of capacitance
over all conditions and the ESR should be less than 80mΩ.
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
board layout will result in very good stability. As the value
of CCPO controls the amount of output ripple, the value
of CVIN controls the amount of ripple present at the input
pin (VIN). The LTC3220/LTC3220-1 input current will be
relatively constant while the charge pump is either in the
input charging phase or the output charging phase but will
drop to zero during the clock nonoverlap times. Since the
nonoverlap time is small (~25ns), these missing “notches”
will result in only a small perturbation on the input power
supply line. Note that a higher ESR capacitor such as tan-
talum will have higher input noise due to the higher ESR.
Therefore, ceramic capacitors are recommended for low
ESR. Input noise can be further reduced by powering the
LTC3220/LTC3220-1 through a very small series inductor
as shown in Figure 4. A 10nH inductor will reject the fast
current notches, thereby presenting a nearly constant
current load to the input power supply. For economy, the
10nH inductor can be fabricated on the PC board with
about 1cm (0.4") of PC board trace.
applicaTions inForMaTion
Figure 4. 10nH Inductor Used for Input Noise Reduction
(Approximately 1cm of Board Space)
VBAT
3220 F04
LTC3220
LTC3220-1
GND
LT03220/LTC322O'1
LTC3220/LTC3220-1
16
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Flying Capacitor Selection
Warning: Polarized capacitors such as tantalum or alumi-
num should never be used for the flying capacitors since
their voltage can reverse upon start-up of the LTC3220/
LTC3220-1. Ceramic capacitors should always be used
for the flying capacitors.
The flying capacitors control the strength of the charge
pump. In order to achieve the rated output current it is
necessary to have at least 1.6µF of capacitance for each of
the flying capacitors. Capacitors of different materials lose
their capacitance with higher temperature and voltage at
different rates. For example, a ceramic capacitor made of
X7R material will retain most of its capacitance from –40°C
to 85°C, whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range. Z5U and Y5V
capacitors may also have a very poor voltage coefficient
causing them to lose 60% or more of their capacitance when
the rated voltage is applied. Therefore, when comparing
different capacitors, it is often more appropriate to compare
the amount of achievable capacitance for a given case size
rather than comparing the specified capacitance value. For
example, over rated voltage and temperature conditions, a
1µF, 10V, Y5V ceramic capacitor in a 0603 case may not
provide any more capacitance than a 0.22µF, 10V, X7R
available in the same case. The capacitor manufacturer’s
data sheet should be consulted to determine what value
of capacitor is needed to ensure minimum capacitances
at all temperatures and voltages.
Table 2 shows a list of ceramic capacitor manufacturers
and how to contact them:
Table 2. Recommended Capacitor Vendors
AVX www.avxcorp.com
Kemet www.kemet.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Vishay www.vishay.com
Layout Considerations and Noise
The LTC3220/LTC3220-1 have been designed to minimize
EMI. However due to their high switching frequency and the
transient currents produced by the LTC3220/LTC3220-1,
careful board layout is necessary. A true ground plane and
short connections to all capacitors will improve perfor-
mance and ensure proper regulation under all conditions.
The flying capacitor pins C1P, C2P, C1M and C2M have
controlled edge rate waveforms. The large dV/dt on these
pins can couple energy capacitively to adjacent PCB runs.
Magnetic fields can also be generated if the flying capacitors
are not close to the LTC3220/LTC3220-1 (i.e., the loop
area is large). To decouple capacitive energy transfer, a
Faraday shield may be used. This is a grounded PCB trace
between the sensitive node and the LTC3220/LTC3220-1
pins. For a high quality AC ground, it should be returned
to a solid ground plane that extends all the way to the
LTC3220/LTC3220-1.
applicaTions inForMaTion
LTC3220/LTC3220—1 PLED VLED ILED VLED h PIN VIN II m VIN PLED VLED ILED VLED PIN VIN II F” V‘N @ VLED ILED VLED Pm VIN 'w VIN L7HEJWEGR 1 7
LTC3220/LTC3220-1
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Power Efficiency
To calculate the power efficiency (η) of an LED driver chip,
the LED power should be compared to the input power.
The difference between these two numbers represents
lost power whether it is in the charge pump or the current
sources. Stated mathematically, the power efficiency is
given by:
η= PLED
P
IN
(4)
The efficiency of the LTC3220/LTC3220-1 depends upon
the mode in which it is operating. Recall that the LTC3220/
LTC3220-1 operate as pass switches, connecting VIN to
CPO, until dropout is detected at the ILED pin. This feature
provides the optimum efficiency available for a given input
voltage and LED forward voltage. When it is operating as
a switch, the efficiency is approximated by:
η= PLED
PIN
=VLED •ILED
VIN •IIN
=VLED
VIN
(5)
since the input current will be very close to the sum of
the LED currents.
At moderate to high output power, the quiescent current of
the LTC3220/LTC3220-1 is negligible and the expression
above is valid.
Once dropout is detected at any LED pin, the LTC3220/
LTC3220-1 enable the charge pump in 1.5x mode.
applicaTions inForMaTion
In 1.5x boost mode, the efficiency is similar to that of a
linear regulator with an effective input voltage of 1.5 times
the actual input voltage. This is because the input current
for a 1.5x charge pump is approximately 1.5 times the
load current. In an ideal 1.5x charge pump, the power
efficiency would be given by:
ηIDEAL =PLED
PIN
=VLED •ILED
VIN •1.5 •ILED
=VLED
1.5 •VIN
Similarly, in 2x boost mode, the efficiency is similar to
that of a linear regulator with an effective input voltage
of 2 times the actual input voltage. In an ideal 2x charge
pump, the power efficiency would be given by:
ηIDEAL =PLED
PIN
=VLED •ILED
VIN •2•ILED
=VLED
2•VIN
Thermal Management
For higher input voltages and maximum output current,
there can be substantial power dissipation in the LTC3220/
LTC3220-1. If the junction temperature increases above
approximately 150°C, the thermal shutdown circuitry will
automatically deactivate the output current sources and
charge pump. To reduce maximum junction temperature,
a good thermal connection to the PC board is recom-
mended. Connecting the Exposed Pad to a ground plane
and maintaining a solid ground plane under the device
will reduce the thermal resistance of the package and PC
board considerably.
LTC322O/LTC3220_1 Pun-$1;
LTC3220/LTC3220-1
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package DescripTion
PF Package
28-Lead UTQFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1759 Rev Ø)
4.00 ± 0.10
4.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.5
2827
1
2
BOTTOM VIEW—EXPOSED PAD
2.64 ± 0.10
2.40 REF
2.64 ± 0.10
2.64 ± 0.05
2.64 ± 0.05
0.55 ± 0.05 R = 0.10
TYP
R = 0.05
TYP
0.20 ± 0.05
0.40 BSC
0.127 REF
0.00 – 0.05
(PF28) UTQFN 0907
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.20 ±0.05
0.40 BSC
2.40 REF
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.25 × 45°
CHAMFER
LTC3220/LTC3220—1 L7 LJUW 19
LTC3220/LTC3220-1
19
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
D 06/15 Modified REG0, Command Byte table 12
(Revision history begins at Rev D)
LTC3220/LTC3220—1 r'h r'h f 1-— f 1—— —> —> u”— 2 Linear Technology Corporation 1630 MccanhyrBlvd" Milpitarsr 9A 95035-7417
LTC3220/LTC3220-1
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007
LT 0715 REV D • PRINTED IN USA
relaTeD parTs
PART NUMBER DESCRIPTION COMMENTS
LTC3205 250mA, 1MHz, Multi-Display LED Controller VIN: 2.8V to 4.5V, VOUT(MAX) = 5.5V, IQ = 50µA, ISD < 1µA, QFN Package
LTC3206 400mA, 800kHz, Multi-Display LED Controller VIN: 2.8V to 4.5V, VOUT(MAX) = 5.5V, IQ = 50µA, ISD < 1µA, QFN Package
LTC3207 600mA Universal Multi-Output LED/CAM Driver VBAT: 2.9V to 5.5V, 12 Universal Individually Controlled LED Drivers, One
Camera Driver, 4mm × 4mm QFN Package
LTC3208 High Current Software Configurable Multi-Display
LED Controller
VIN: 2.9V to 4.5V, VOUT(MAX) = 5.5V, IQ = 250µA, ISD < 3µA, 17 Current
Sources (MAIN, SUB, RGB, CAM, AUX), 5mm × 5mm QFN Package
LTC3209-1/
LTC3209-2
600mA MAIN/Camera/AUX LED Controller VIN: 2.9V to 4.5V, IQ = 400mA, Up to 94% Efficiency, 4mm × 4mm
QFN-20 Package
LTC3210 MAIN/CAM LED Controller in 3mm × 3mm QFN VIN: 2.9V to 4.5V, IQ = 400µA, 3-Bit DAC Brightness Control for MAIN and
CAM LEDs, 3mm × 3mm QFN Package
LTC3210-1 MAIN/CAM LED Controller with 64-Step
Brightness Control
6-Bit DAC Brightness Control for MAIN and 3-Bit Brightness Control for CAM,
3mm × 3mm QFN Package
LTC3210-2 MAIN/CAM LED Controller with 32-Step
Brightness Control
Drives 4 MAIN LEDs, 3mm × 3mm QFN Package
LTC3210-3 MAIN/CAM LED Controller with 32-Step
Brightness Control
Drives 3 MAIN LEDs, 3mm × 3mm QFN Package
LTC3212 RGB LED Driver and Charge Pump Drives RGB LEDs, 25mA/LED × 3, VIN Range: 2.9V to 4.5V, 2mm × 3mm DFN
Package
LTC3214 500mA Camera LED Charge Pump VIN: 2.9V to 4.5V, Single Output, 3mm × 3mm DFN Package
LTC3215 700mA Low Noise High Current LED
Charge Pump
VIN: 2.9V to 4.4V, VOUT(MAX) = 5.5V, IQ = 300µA, ISD < 2.5µA, DFN Package
LTC3216 1A Low Noise High Current LED Charge Pump
with Independent Flash/Torch Current Control
VIN: 2.9V to 4.4V, VOUT(MAX) = 5.5V, IQ = 300µA, ISD < 2.5µA, DFN Package
LTC3217 600mA Low Noise Multi-LED Camera Light VIN: 2.9V to 4.4V, IQ = 400µA, Four 100mA Outputs, QFN Package
LTC3218 400mA Single-Wire Camera LED Charge Pump 91% Efficiency, VIN Range: 2.9V to 4.5V, 2mm × 3mm DFN Package,
High Side Current Sense
LTC3219 250mA Universal Multi-Output LED Driver VBAT 2.9V to 5.5V, Nine Universal Individually Controlled LED Drivers,
3mm × 3mm QFN Package
LTC3440/LTC3441 600mA/1.2A IOUT, 2MHz/1MHz, Synchronous
Buck-Boost DC/DC Converter
VIN: 2.4V to 5.5V, VOUT(MAX) = 5.25V, IQ = 25µA/50µA, ISD <1µA,
MS/DFN Packages
LTC3443 600mA/1.2A IOUT, 600kHz, Synchronous
Buck-Boost DC/DC Converter
VIN: 2.4V to 5.5V, VOUT(MAX) = 5.25V, IQ = 28µA, ISD <1µA, DFN Package
LTC3453 1MHz, 800mA Synchronous Buck-Boost High
Power LED Driver
VIN(MIN): 2.7V to 5.5V, VIN(MAX): 2.7V to 4.5V, IQ = 2.5mA, ISD < 6µA,
QFN Package
Typical applicaTion
DVCC
I2C
0.1µF
C1P
VIN
DVCC
SCL/SDA
VIN
2.2µF
2.2µF 2.2µF
CPO
ULED1-18
C1M
GND
C2P
LTC3220
LTC3220-1
C2M
4.7µF
CAM
3220 TA02
18
RST
MAIN RGB
BLINKING
STATUS
INDICATORS GPO 1, 2, 3 VIN
GPO4
100k
60mA
Cellular Phone Multi-Display LED Controller with Auxiliary Current Source Output
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3220