OPA316, 2316(S), 4316 Datasheet by Texas Instruments

Datasheet Feedback/Errors

r.- 1!. I2 X 9 I TEXAS INSTRUMENTS PM» W‘

-45

135

180

225

270

±20

100

120

1 10 100 1k 10k 100k 1M 10M 100M

Phase (º)

Gain (dB)

Frequency (Hz)

VS = “2.75 V

VS = “0.9 V

C006

Phase

Gain

VS = “2.75 V

VS = “0.9 V

RGRF

VIN

VOUT

= 1 +

OUT

1 + sR C

1 1

( (

((

2pR C

1 1

f =

-3 dB

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

OPAx316 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier

1 Features

1• Unity-Gain Bandwidth: 10 MHz

• Low IQ: 400 µA/ch

• Wide Supply Range: 1.8 V to 5.5 V

• Low Noise: 11 nV/√Hz at 1 kHz

• Low Input Bias Current: ±5 pA

• Offset Voltage: ±0.5 mV

• Unity-Gain Stable

• Internal RFI-EMI Filter

• Shutdown Version: OPA2316S

• Extended Temperature Range: –40°C to +125°C

2 Applications

• Battery-Powered Instruments:

– Consumer, Industrial, Medical

– Notebooks, Portable Media Players

• Sensor Signal Conditioning

• Automotive Applications

• Barcode Scanners

• Active Filters

• Audio

3 Description

The OPAx316 family of single, dual, and quad

operational amplifiers represents a new generation of

general-purpose, low-power operational amplifiers.

Featuring rail-to-rail input and output swings, low

quiescent current (400 μA/ch typical) combined with a

wide bandwidth of 10 MHz and very-low noise

(11 nV/√Hz at 1 kHz) makes this family attractive for

a variety of applications that require a good balance

between cost and performance. The low input bias

current supports those operational amplifiers to be

used in applications with MΩsource impedances.

The robust design of the OPAx316 provide ease-of-

use to the circuit designer—a unity-gain stable,

integrated RFI-EMI rejection filter, no phase reversal

in overdrive condition, and high electrostatic

discharge (ESD) protection (4-kV HBM).

These devices are optimized for low-voltage

operation as low as 1.8 V (±0.9 V) and up to 5.5 V

(±2.75 V). This latest addition of low-voltage CMOS

operational amplifiers, in conjunction with the

OPAx313 and OPAx314 provide a family of

bandwidth, noise, and power options to meet the

needs of a wide variety of applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

OPA316 SC-70 (5) 1.25 mm × 2.00 mm

SOT-23 (5) 1.60 mm × 2.90 mm

OPA2316

DFN (8) 3.00 mm × 3.00 mm

MSOP, VSSOP (8) 3.00 mm × 3.00 mm

SOIC (8) 3.91 mm × 4.90 mm

OPA2316S MSOP, VSSOP (10) 3.00 mm × 3.00 mm

X2QFN (10) 1.50 mm × 2.00 mm

OPA4316 TSSOP (14) 4.40 mm × 5.00 mm

SOIC (14) 8.65 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

SPACE Single-Pole, Low-Pass Filter Low-Supply Current (400 µA/ch) for 10-MHz Bandwidth

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information: OPA316 .................................. 6

6.5 Thermal Information: OPA2316 ................................ 7

6.6 Thermal Information: OPA2316S.............................. 7

6.7 Thermal Information: OPA4316 ................................ 8

6.8 Electrical Characteristics........................................... 9

6.9 Typical Characteristics............................................ 11

7 Detailed Description............................................ 17

7.1 Overview ................................................................. 17

7.2 Functional Block Diagram ....................................... 17

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 20

8 Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Application .................................................. 22

9 Power Supply Recommendations...................... 25

10 Layout................................................................... 26

10.1 Layout Guidelines ................................................. 26

10.2 Layout Example .................................................... 26

11 Device and Documentation Support ................. 27

11.1 Documentation Support ........................................ 27

11.2 Related Links ........................................................ 27

11.3 Receiving Notification of Documentation Updates 27

11.4 Community Resources.......................................... 27

11.5 Trademarks........................................................... 27

11.6 Electrostatic Discharge Caution............................ 27

11.7 Glossary................................................................ 27

12 Mechanical, Packaging, and Orderable

Information ........................................................... 28

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (May 2016) to Revision F Page

• Added SOIC (14) / OPA4316 body size information to Device Information table ................................................................. 1

• Added D package to PW package pinout drawing ................................................................................................................ 4

• Added D (SOIC) thermal information to Thermal Information: OPA4316 table .................................................................... 8

Changes from Revision D (December 2014) to Revision E Page

• Added new "RUG" package ................................................................................................................................................... 1

Changes from Revision C (October 2014) to Revision D Page

• Added Shutdown section to Electrical Characteristics table ............................................................................................... 10

• Added Related Documentation section ............................................................................................................................... 27

Changes from Revision B (August 2014) to Revision C Page

• Updated devices and packages in Device Information table ................................................................................................ 1

• Added thermal information for OPA2316S and OPA4316 ..................................................................................................... 7

Changes from Revision A (April 2014) to Revision B Page

• Added OPA2316 to the Device Information table................................................................................................................... 1

• Added thermal information for OPA2316 .............................................................................................................................. 7

• Added channel separation to Electrical Characteristics ........................................................................................................ 9

• Added GBP instead of UGB in the Electrical Characteristics ................................................................................................ 9

• Added Channel Separation vs Frequency plot..................................................................................................................... 16

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Changes from Original (April 2014) to Revision A Page

• Changed status from preview to production .......................................................................................................................... 1

‘5‘ TEXAS INSTRUMENTS j j C C C ““““ ,,,,,, , ﬂ , ﬂ , , , , , wwwwwww \\\\\\\\ , , , , , , , , , j j j j j j j M E7? C C IIIIIIIIIII C C C C C C C j j j j 2% C C C C

OUTD

-IND

+IND

V-

OUTA

-INA

+INA

V+

+INC

-INC

OUTC

+INB

-INB

OUTB

V+

OUTB

-INB

+INB

OUTA

-INA

+INA

V-

V±

V+

SHDN A

SHDN B

±IN A

±IN B

+IN B

+IN A

OUT A

OUT B

456

OUTA

-INA

+INA

V-

V+

OUTB

-INB

+INB

Exposed

Thermal

DiePad

Underside(2)

V+

-IN

OUT

V-

+IN

V+

OUT B

–IN B

+IN B

SHDN B

OUT A

–IN A

+IN A

V–

SHDN A

V+

OUT

+IN

V-

-IN

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

5 Pin Configuration and Functions

DCK Package

5-Pin SC70

Top View

DBV Package

5-Pin SOT-23

Top View

DRG Package

8-Pin DFN

Top View

Pitch: 0.5 mm.

Connect thermal pad to V–. Pad size: 2.00 mm × 1.20 mm.

D, DGK Packages

8-Pin MSOP, SO

Top View

DGS Package

10-Pin MSOP

Top View

RUG Package

10-Pin QFN

Top View

D, PW Packages

14-Pin SOIC, TSSOP

Top View

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Pin Functions

DESCRIPTION

NAME

OPA316 OPA2316 OPA2316S OPA4316

DBV DCK D, DGK,

DRG DGS RUG PW D

+IN 3 1 — — — — — Noninverting input

+IN A — — 3 3 10 3 3 Noninverting input

+IN B — — 5 7 4 5 5 Noninverting input

+IN C — — — — — 10 10 Noninverting input

+IN D — — — — — 12 12 Noninverting input

–IN 4 3 — — — — — Inverting input

–IN A — — 2 2 9 2 2 Inverting input

–IN B — — 6 8 5 6 6 Inverting input

–IN C — — — — — 9 9 Inverting input

–IN D — — — — — 13 13 Inverting input

OUT 1 4 — — — — — Output

OUT A — — 1 1 8 1 1 Output

OUT B — — 7 9 6 7 7 Output

OUT C — — — — — 8 8 Output

OUT D — — — — — 14 14 Output

SHDN

A— — — 5 2 — — Shutdown (logic low), enable (logic high)

SHDN

B— — — 6 3 — — Shutdown (logic low), enable (logic high)

V+ 5 5 8 10 7 4 4 Positive supply

V– 2 2 4 4 1 11 11 Negative supply or ground (for single-supply

operation)

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply

rails to 10 mA or less.

(3) Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1)

MIN MAX UNIT

Supply voltage 7 V

Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V

Differential (V+) – (V–) + 0.2 V

Current(2) –10 10 mA

Output short-circuit(3) Continuous

TAOperating temperature –55 150 °C

TJJunction temperature 150 °C

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted).

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).

MIN MAX UNIT

VSSupply voltage 1.8 5.5 V

Specified temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

6.4 Thermal Information: OPA316

THERMAL METRIC(1)

OPA316

UNITDBV (SOT23) DCK (SC70)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance(2) 221.7 263.3 °C/W

RθJC(top) Junction-to-case(top) thermal resistance(3) 144.7 75.5 °C/W

RθJB Junction-to-board thermal resistance(4) 49.7 51 °C/W

ψJT Junction-to-top characterization parameter(5) 26.1 1 °C/W

ψJB Junction-to-board characterization parameter(6) 49 50.3 °C/W

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Thermal Information: OPA316 (continued)

THERMAL METRIC(1)

OPA316

UNITDBV (SOT23) DCK (SC70)

5 PINS 5 PINS

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Thermal Information: OPA2316

THERMAL METRIC(1)

OPA2316

UNITD (SO) DGK (MSOP) DRG (DFN)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance(2) 127.2 186.6 56.3 °C/W

RθJC(top) Junction-to-case(top) thermal resistance(3) 71.6 78.8 72.2 °C/W

RθJB Junction-to-board thermal resistance(4) 68.2 107.9 31 °C/W

ψJT Junction-to-top characterization parameter(5) 22 15.5 2.3 °C/W

ψJB Junction-to-board characterization parameter(6) 67.6 106.3 21.2 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A 10.9 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.6 Thermal Information: OPA2316S

THERMAL METRIC(1)

OPA2316S

UNITDGS (MSOP) QFN (RUG)

10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance(2) 189.6 158 °C/W

RθJC(top) Junction-to-case(top) thermal resistance(3) 73.9 52 °C/W

RθJB Junction-to-board thermal resistance(4) 110.7 88 °C/W

ψJT Junction-to-top characterization parameter(5) 13.4 1 °C/W

ψJB Junction-to-board characterization parameter(6) 109.1 87 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.7 Thermal Information: OPA4316

THERMAL METRIC(1)

OPA4316

UNITPW (TSSOP) D (SOIC)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance(2) 117.2 87.0 °C/W

RθJC(top) Junction-to-case(top) thermal resistance(3) 46.2 44.4 °C/W

RθJB Junction-to-board thermal resistance(4) 58.9 41.7 °C/W

ψJT Junction-to-top characterization parameter(5) 4.9 11.6 °C/W

ψJB Junction-to-board characterization parameter(6) 58.3 41.4 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

(1) Third-order filter; bandwidth = 80 kHz at –3 dB.

6.8 Electrical Characteristics

VS(total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.

at TA= 25°C, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

VOS Input offset voltage VS= 5 V ±0.5 ±2.5 mV

VS= 5 V, TA= –40°C to 125°C ±3.5 mV

dVOS/dT Drift VS= 5 V, TA= –40°C to 125°C ±2 ±10 μV/°C

PSRR vs power supply VS= 1.8 V – 5.5 V, VCM = (V–) ±30 ±150 µV/V

VS= 1.8 V – 5.5 V, VCM = (V–), TA= –40°C to 125°C ±250 µV/V

Channel separation, dc At dc 10 µV/V

INPUT VOLTAGE RANGE

VCM Common-mode voltage VS= 1.8 V to 2.5 V (V–) – 0.2 (V+) V

VS= 2.5 V to 5.5 V (V–) – 0.2 (V+) + 0.2 V

CMRR Common-mode rejection ratio

VS= 1.8 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,

TA= –40°C to 125°C 70 86 dB

VS= 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,

TA= –40°C to 125°C 76 90 dB

VS= 1.8 V, VCM = –0.2 V to 1.8 V,

TA= –40°C to 125°C 57 72 dB

VS= 5.5 V, VCM = –0.2 V to 5.7 V,

TA= –40°C to 125°C 65 80 dB

INPUT BIAS CURRENT

IBInput bias current ±5 ±15 pA

TA= –40°C to 125°C ±15 nA

IOS Input offset current ±2 ±15 pA

TA= –40°C to 125°C ±8 nA

NOISE

EnInput voltage noise (peak-to-peak) VS= 5 V, f = 0.1 Hz to 10 Hz 3 μVPP

enInput voltage noise density VS= 5 V, f = 1 kHz 11 nV/√Hz

inInput current noise density f = 1 kHz 1.3 fA/√Hz

INPUT IMPEDANCE

ZID Differential 2 || 2 1016Ω|| pF

ZIC Common-mode 2 || 4 1011Ω|| pF

OPEN-LOOP GAIN

AOL Open-loop voltage gain

VS= 1.8 V, (V–) + 0.04 V < VO< (V+) – 0.04 V,

RL= 10 kΩ94 100 dB

VS= 5.5 V, (V–) + 0.05 V < VO< (V+) – 0.05 V,

RL= 10 kΩ104 110 dB

VS= 1.8 V, (V–) + 0.1 V < VO< (V+) – 0.1 V,

RL= 2 kΩ90 96 dB

VS= 5.5 V, (V–) + 0.15 V < VO< (V+) – 0.15 V,

RL= 2 kΩ100 106 dB

VS= 5.5 V, (V–) + 0.05 V < VO< (V+) – 0.05 V,

RL= 10 kΩ, TA= –40°C to 125°C 86 dB

VS= 5.5 V, (V–) + 0.15 V < VO< (V+) – 0.15 V,

RL= 2 kΩ, TA= –40°C to 125°C 84 dB

FREQUENCY RESPONSE

GBP Gain bandwidth product VS= 5 V, G = +1 10 MHz

φmPhase margin VS= 5 V, G = +1 60 Degrees

SR Slew rate VS= 5 V, G = +1 6 V/μs

tSSettling time To 0.1%, VS= 5 V, 2-V step , G = +1, CL= 100 pF 1 μs

To 0.01%, VS= 5 V, 2-V step , G = +1, CL= 100 pF 1.66 μs

tOR Overload recovery time VS= 5 V, VIN × gain = VS0.3 μs

THD + N Total harmonic distortion + noise(1) VS= 5 V, VO= 0.5 VRMS, G = +1, f = 1 kHz 0.0008%

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Electrical Characteristics (continued)

VS(total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.

at TA= 25°C, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) Ensured by design and characterization; not production tested.

(3) Enable time (tON) and disable time (tOFF) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(4) Full shutdown refers to the dual OPA2316S having both channels A and B disabled (SHDN_A = SHDN_B = VS–). For partial shutdown,

only one SHDN pin is exercised; in partial mode, the internal biasing and oscillator remain operational and the enable time is shorter.

OUTPUT

VOVoltage output swing from supply

rails

VS= 1.8 V, RL= 10 kΩ, TA= –40°C to 125°C 15 mV

VS= 5.5 V, RL= 10 kΩ, TA= –40°C to 125°C 30 mV

VS= 1.8 V, RL= 2 kΩ, TA= –40°C to 125°C 60 mV

VS= 5.5 V, RL= 2 kΩ, TA= –40°C to 125°C 120 mV

ISC Short-circuit current VS= 5 V ±50 mA

ZOOpen-loop output impedance VS= 5 V, f = 10 MHz 250 Ω

POWER SUPPLY

VSSpecified voltage 1.8 5.5 V

IQQuiescent current per amplifier VS= 5 V, IO= 0 mA, TA= –40°C to 125°C 400 500 µA

Power-on time VS= 0 V to 5.5 V 200 µs

SHUTDOWN (VS= 1.8 V to 5.5 V)(2)

IQSD Quiescent current, per device All amplifiers disabled, SHDN = VS– 0.01 1 µA

One amplifier disabled (OPA2316S) 345 µA

VIH High voltage (enabled) Amplifier enabled (V+) – 0.5 V

VIL Low voltage (disabled) Amplifier disabled (V–) + 0.2 V

tON Amplifier enable time(3) Full shutdown, G = 1, VOUT = 0.9 × VS/ 2(4) 13 µs

Partial shutdown, G = 1, VOUT = 0.9 × VS/ 2(4) 10 µs

tOFF Amplifier disable time(3) G = 1, VOUT = 0.1 × VS/ 2 5 µs

SHDN pin input bias current (per

pin)

VIH = 5 V 3.5 pA

VIL = 0 V 2.5 pA

TEMPERATURE

Specified temperature –40 125 °C

TAOperating temperature –55 150 °C

Tstg Storage temperature –65 150 °C

TEXAS INSTRUMENTS

±2500

±2000

±1500

±1000

±500

500

1000

1500

2000

2500

0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

VOS (V)

VSUPPLY (V)

C001

VS = ±2.75 V

VS = ±0.9 V

-45

135

180

225

270

±20

100

120

1 10 100 1k 10k 100k 1M 10M 100M

Phase (º)

Gain (dB)

Frequency (Hz)

VS = “2.75 V

VS = “0.9 V

C006

Phase

Gain

VS = “2.75 V

VS = “0.9 V

±2500

±2000

±1500

±1000

±500

500

1000

1500

2000

2500

±75 ±50 ±25 0 25 50 75 100 125 150

VOS (V)

Temperature (ƒC)

C001

±2500

±2000

±1500

±1000

±500

500

1000

1500

2000

2500

±3 ±2 ±1 0 1 2 3

VOS (V)

VCM (V)

C001

VCM = -2.95 V

N-

Channel

P-

Channel

Transition

VCM = 2.95 V

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

Percentage of Amplifiers (%)

Offset Voltage (mV)

C013

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

Percentage of Amplifiers (%)

Offset Voltage Drift (µV/ƒC)

C013

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

6.9 Typical Characteristics

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

Distribution taken from 12551 amplifiers

Figure 1. Offset Voltage Production Distribution

TA= –40°C to +125°C, Distribution taken from 70 amplifiers

Figure 2. Offset Voltage Drift Distribution

9 typical units shown

Figure 3. Offset Voltage vs Temperature

V+ = 2.75 V, V– = –2.75 V, 9 typical units shown

Figure 4. Offset Voltage vs Common-Mode Voltage

V+ = 0.9 V to 2.75 V, V– = –0.9 V to –2.75 V,

9 typical units shown

Figure 5. Offset Voltage vs Power Supply

VCM < (V+) – 1.4 V

Figure 6. Open-Loop Gain and Phase vs Frequency

l TEXAS INSTRUMENTS

-3

-2

-1

0 10 20 30 40 50 60

Vout (V)

Iout (mA)

C001

-40°C

125°C

25°C

85°C

-40°C

25°C

125°C

85°C

100

120

1 10 100 1k 10k 100k 1M

Common-Mode Rejection Ratio (dB),

Power-Supply Rejection Ratio (dB)

Frequency (Hz)

PSRR

CMRR

C011

100

1000

10000

100000

±75 ±50 ±25 0 25 50 75 100 125 150

Input Bias Current and

Input Offset Current (pA)

Temperature (ƒC)

C001

B+

IB -

Ios

-20

-15

-10

-5

10k 100k 1M 10M 100M

Gain (dB)

Frequency (Hz)

G = +1

G = +10

G = -1

C007

-50

-25

100

±75 ±50 ±25 0 25 50 75 100 125 150

AOL (µV/V)

Temperature (ƒC)

C001

VS = 1.8 V

VS = 5.5 V

-50

-25

100

±75 ±50 ±25 0 25 50 75 100 125 150

AOL (µV/V)

Temperature (ƒC)

C001

VS = 5.5 V

VS = 1.8 V

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Typical Characteristics (continued)

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

RL= 10 kΩ

Figure 7. Open-Loop Gain vs Temperature

RL= 2 kΩ

Figure 8. Open-Loop Gain vs Temperature

Figure 9. Closed-Loop Gain vs Frequency Figure 10. Input Bias and Offset Current vs Temperature

V+ = 2.75 V, V– = –2.75 V

Figure 11. Output Voltage Swing vs Output Current Figure 12. CMRR and PSRR vs Frequency

(Referred to Input)

l TEXAS INSTRUMENTS

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Voltage Noise (nV/rtHz)

Common-Mode Voltage (V)

C039

100

1000

0.1 1 10 100 1k 10k 100k

9ROWDJH1RLVH'HQVLW\Q9¥+]

Frequency (Hz)

C015

-20

100

±75 ±50 ±25 0 25 50 75 100 125 150

Power-Supply Rejection Ratio (µV/V)

Temperature (ƒC)

C001

1 V/div

Time (1 s/div)

C014

Peak-to-Peak Noise = V

RMS

6.6 = 3 V

±200

±150

±100

±50

100

150

200

±75 ±50 ±25 0 25 50 75 100 125 150

Common-Mode Rejection Ratio (µV/V)

Temperature (ƒC)

C001

VS = 1.8 V, (V-) - 9”9CM ”9- 1.4 V

VS = 5.5 V, (V-) - 9”9CM ”9- 1.4 V

±1000

±750

±500

±250

250

500

750

1000

±75 ±50 ±25 0 25 50 75 100 125 150

Common-Mode Rejection Ratio (µV/V)

Temperature (ƒC)

C001

VS = 1.8 V, (V-) - 9”9CM ”9

VS = 5.5 V, (V-) - 9”9CM ”99

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Typical Characteristics (continued)

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

Figure 13. CMRR vs Temperature (Narrow Range) Figure 14. CMRR vs Temperature (Wide Range)

Figure 15. PSRR vs Temperature Figure 16. 0.1-Hz to 10-Hz Input Voltage Noise

Figure 17. Input Voltage Noise Spectral Density vs

Frequency

ƒ = 1 kHz

Figure 18. Input Voltage Noise vs Common-Mode Voltage

l TEXAS INSTRUMENTS

100

10k

1 10 100 1k 10k 100k 1M 10M 100M 1000M

ZO ()

Frequency (Hz)

C024

0p 100p 200p 300p

Overshoot (%)

Capacitive Load (F)

C025

RI= 1 kohm

VIN = 100 mVpp

+ 2.75 V

±2.75 V

Device

RF= 1 kohm

250

275

300

325

350

375

400

425

450

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

IQ (µA)

Supply Voltage (V)

C001

350

375

400

425

450

±75 ±50 ±25 0 25 50 75 100 125 150

IQ (µA)

Temperature (ƒC)

C001

VS = 5.5 V

VS = 1.8 V

-120

-100

-80

-60

0.0001

0.001

0.01

0.1

10 100 1k 10k 100k

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Frequency (Hz)

G = +1 V/V, RL = 10 k

G = +1 V/V, RL = 2 k

G = -1 V/V, RL = 10 k

G = -1 V/V, RL = 2 k

C017

G = +1 V/V, RL N

G = +1 V/V, RL N

G = -1 V/V, RL N

G = -1 V/V, RL N

-140

-120

-100

-80

-60

-40

0.00001

0.0001

0.001

0.01

0.1

0.001 0.01 0.1 1 10

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Output Amplitude (VRMS)

G = +1 V/V, RL = 2 k

G = -1 V/V, RL = 10 k

G = -1 V/V, RL = 2 k

C018

G = +1 V/V, RL N

G = +1 V/V, RL N

G = -1 V/V, RL N

G = -1 V/V, RL N

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Typical Characteristics (continued)

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

BW = 80 kHz, VOUT = 0.5 VRMS

Figure 19. THD + N vs Frequency

ƒ = 1 kHz, BW = 80 kHz

Figure 20. THD + N vs Amplitude

Figure 21. Quiescent Current vs Supply Voltage Figure 22. Quiescent Current vs Temperature

Figure 23. Open-Loop Output Impedance vs Frequency

V+ = 2.75 V, V– = –2.75 V, G = –1 V/V

Figure 24. Small-Signal Overshoot vs Load Capacitance

l TEXAS INSTRUMENTS

Output Voltage (20 mV/div)

Time (200 ns/div)

CL = 10 pF

CL = 100 pF

C030

VIN = 100 mVpp

+ 2.75 V

±2.75 V

Device

CL = 10 pF

CL = 100 pF

200 mV/div

Time (100 ns/div)

C031

VIN = 1 Vpp

+ 2.75 V

±2.75 V

Device

VOUT

VIN

500 mV/div

Time (100 ns/div)

C028

VOUT

VIN

RF= 10 kohmRI= 1 kohm

VOUT

VIN = 1 Vpp

+ 2.75 V

±2.75 V

Device

Saturated

Recovering

Slewing

0 V

-1 V

5.5 V

500 mV/div

Time (100 ns/div)

C029

VOUT

VIN

RF= 10 kohmRI= 1 kohm

VOUT

VIN = 1 Vpp

+ 2.75 V

±2.75 V

Device

Saturated

Recovering

Slewing

0 V

1 V

-5.5 V

0p 100p 200p 300p

Overshoot (%)

Capacitive Load (F)

C026

VIN = 100 mVpp

+ 2.75 V

±2.75 V

Device

1 V/div

Time (100 s/div)

C027

VOUT

VIN

6.1 VPP

Sine Wave

+VOUT

+ 2.75 V

±2.75 V

Device

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Typical Characteristics (continued)

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

V+ = 2.75 V, V– = –2.75 V , G = +1 V/V, RL= 1 kΩ

Figure 25. Small-Signal Overshoot vs Load Capacitance

V+ = 2.75 V, V– = –2.75 V

Figure 26. No Phase Reversal

V+ = 2.75 V, V– = –2.75 V , G = –10 V/V

Figure 27. Positive Overload Recovery

V+ = 2.75 V, V– = –2.75 V, G = –10 V/V

Figure 28. Negative Overload Recovery

V+ = 2.75 V, V– = –2.75 V, G = +1 V/V

Figure 29. Small-Signal Step Response

V+ = 2.75 V, V– = –2.75 V, CL= 100 pF, G = +1 V/V

Figure 30. Large-Signal Step Response

l TEXAS INSTRUMENTS me 10M

100

10M 100M 1G 10G

EMIRR IN+ (dB)

Frequency (Hz)

C036

±120

±100

±80

±60

±40

±20

10 100 1k 10k 100k 1M 10M

Crosstalk (dB)

Frequency (Hz)

C001

±75 ±50 ±25 0 25 50 75 100 125 150

ISC (mA)

Temperature (ƒC)

C001

ISC, Source

ISC, Sink

100k 1M 10M

Output Voltage (VPP)

Frequency (Hz)

C035

VS = 1.8 V

VS = 5 V

VS = 5.5 V

Maximum output voltage without

slew-rate induced distortion.

-40

-20

100

0 0.5 1 1.5 2

Output Delta from Final Value (mV)

Time (s)

C032

0.1% Settling = ±2 mV

-80

-60

-40

-20

0 0.5 1 1.5 2

Output Delta from Final Value (mV)

Time (s)

C033

0.1% Settling = ±2 mV

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Typical Characteristics (continued)

at TA= 25°C, VS= 5.5 V, RL= 10 kΩconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.

CL= 100 pF, G = +1 V/V

Figure 31. Positive Large-Signal Settling Time

CL= 100 pF, G = +1 V/V

Figure 32. Negative Large-Signal Settling Time

Figure 33. Short-Circuit Current vs Temperature Figure 34. Maximum Output Voltage vs

Frequency and Supply Voltage

PRF = –10 dBm

Figure 35. Electromagnetic Interference Rejection Ratio

Referred to Noninverting Input (EMIRR IN+) vs Frequency

V+ = 2.75 V, V– = –2.75 V

Figure 36. Channel Separation vs Frequency

Reference

Current

V+

VIN-

VIN+

(Ground)

VBIAS2

VBIAS1 Class AB

Control

Circuitry

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

7 Detailed Description

7.1 Overview

The OPA316 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices operate

from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The

class AB output stage is capable of driving less than or equal to 10-kΩloads connected to any point between V+

and ground. The input common-mode voltage range includes both rails and allows the OPA316 series to be used

in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range,

especially in low-supply applications, and makes them ideal for driving sampling analog-to-digital converters

(ADCs).

The OPA316 family features 10-MHz bandwidth and 6-V/μs slew rate with only 400-μA supply current per

channel, providing good ac performance at very-low power consumption. DC applications are well served with a

very-low input noise voltage of 11 nV/√Hz at 1 kHz, low input bias current (5 pA), and an input offset voltage of

0.5 mV (typical).

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Operating Voltage

The OPAx316 operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In addition,

many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or

temperature are illustrated in the Typical Characteristics graphs.

7.3.2 Rail-to-Rail Input

The input common-mode voltage range of the OPAx316 series extends 200 mV beyond the supply rails for

supply voltages greater than 2.5 V. This performance is achieved with a complementary input stage: an N-

channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block

Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV

above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative

l TEXAS INSTRUMENTS

5 kW

10-mA max

V+

VIN

VOUT

IOVERLOAD

Device

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Feature Description (continued)

supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in

which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the

transition region (both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, up to (V+) – 1 V to

(V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can

be degraded compared to device operation outside this region.

7.3.3 Input and ESD Protection

The OPAx316 incorporates internal ESD protection circuits on all pins. In the case of input and output pins, this

protection primarily consists of current-steering diodes connected between the input and power-supply pins.

These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10

mA as stated in Absolute Maximum Ratings.Figure 37 shows how a series input resistor can be added to the

driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the

value must be kept to a minimum in noise-sensitive applications.

Figure 37. Input Current Protection

7.3.4 Common-Mode Rejection Ratio (CMRR)

CMRR for the OPAx316 is specified in several ways so the user can select the best match for a given

application, as shown in Electrical Characteristics. First, the data sheet gives the CMRR of the device in the

common-mode range below the transition region [VCM < (V+) – 1.4 V]. This specification is the best indicator of

device capability when the application requires use of one of the differential input pairs. Second, the CMRR over

the entire common-mode range is specified at VCM = –0.2 V to 5.7 V for VS= 5.5 V. This last value includes the

variations shown in Figure 4 through the transition region.

7.3.5 EMI Susceptibility and Input Filtering

Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If

conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output can shift from its

nominal value when EMI is present. This shift is a result of signal rectification associated with the internal

semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the signal input

pins are likely to be the most susceptible. The OPA316 operational amplifier family incorporates an internal input

low-pass filter that reduces the amplifier response to EMI. This filter provides both common-mode and

differential-mode filtering. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a

roll-off of 20 dB per decade.

TI developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad

frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational

amplifiers to be directly compared by the EMI immunity. Figure 35 illustrates the results of this testing on the

OPA316 series. For more information, see EMI Rejection Ratio of Operational Amplifiers (SBOA128).

7.3.6 Rail-to-Rail Output

Designed as a low-power, low-noise operational amplifier, the OPAx316 delivers a robust output drive capability.

A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.

For resistive loads of 10-kΩ, the output swings typically to within 30 mV of either supply rail regardless of the

power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the

rails; see the typical characteristic graph Output Voltage Swing vs Output Current (Figure 11).

l TEXAS INSTRUMENTS

VIN

VOUT

V+

10 to

WRLCL

Device

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Feature Description (continued)

7.3.7 Capacitive Load and Stability

The OPAx316 is designed to be used in applications where driving a capacitive load is required. As with all

operational amplifiers, there may be specific instances where the OPAx316 can become unstable. The particular

operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider

when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain

(+1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an

amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output

resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the

phase margin increases as the capacitive loading increases. As a conservative best practice, designing for 25%

overshoot (40° phase margin) provides improved stability over process variations. The equivalent series

resistance (ESR) of some very-large capacitors (CLgreater than 1 μF) is sufficient to alter the phase

characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop

gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when

observing the overshoot response of the amplifier at higher voltage gains. See the typical characteristic graphs,

Small-Signal Overshoot vs Capacitive Load (Figure 24, G = –1 V/V) and Small-Signal Overshoot vs Capacitive

Load (Figure 25, G = +1 V/V).

One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain

configuration is to insert a small resistor (typically 10 Ωto 20 Ω) in series with the output, as shown in Figure 38.

This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible

problem with this technique, however, is that a voltage divider is created with the added series resistor and any

resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output

that reduces the output swing.

Figure 38. Improving Capacitive Load Drive

7.3.8 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated

state to a linear state. The output devices of the operational amplifier enter a saturation region when the output

voltage exceeds the rated operating voltage, either because of the high input voltage or the high gain. After the

device enters the saturation region, the charge carriers in the output devices require time to return back to the

linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified

slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time

and the slew time. The overload recovery time for the OPAx316 is approximately 300 ns.

7.3.9 DFN Package

The OPA2316 (dual version) device uses the DFN style package (also known as SON); this package is a QFN

with contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board

(PCB) space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the

primary advantages of the DFN package is the low, 0.9-mm height. DFN packages are physically small, have a

smaller routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that

is consistent with other commonly-used packages, such as SOIC and MSOP). Additionally, the absence of

external leads eliminates bent-lead issues.

The DFN package can be simply mounted using standard PCB assembly techniques. See QFN/SON PCB

Attachment (SLUA271) , and Quad Flatpack No-Lead Logic Packages (SCBA017).

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

Feature Description (continued)

NOTE

Connect the exposed lead frame die pad on the bottom of the DFN package to the most

negative potential (V–).

7.4 Device Functional Modes

The OPA316, OPA2316, and OPA4316 devices are powered on when the supply is connected. The devices can

be operated as a single-supply operational amplifier or a dual-supply amplifier, depending on the application.

The OPA2316S device has a SHDN (enable) pin function referenced to the negative supply voltage of the

operational amplifier. A logic level high enables the operational amplifier. A valid logic high is defined as voltage

[(V+) – 0.1 V], up to (V+), applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–),

applied to the enable pin. The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative

supply, independent of the positive supply voltage. Connect this pin to a valid high or a low voltage or driven, but

not left as an open circuit.

The logic input is a high-impedance CMOS input. Both inputs are independently controlled. For battery-operated

applications, this feature can be used to greatly reduce the average current and extend battery life.

l TEXAS INSTRUMENTS um %

VIN

VOUT 1

2pRC

f =

-3 dB

R R = R

C C = C

Q = Peaking factor

(Butterworth Q = 0.707)

1 2

RG=

(

2-1

RGRF

VIN

VOUT

= 1 +

OUT

1 + sR C

1 1

( (

((

2pR C

1 1

f =

-3 dB

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 General Configurations

When receiving low-level signals, the device often requires limiting the bandwidth of the incoming signals into the

system. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting pin of the

amplifier, as Figure 39 shows.

Figure 39. Single-Pole Low-Pass Filter

If even more attenuation is needed, the device requires a multiple-pole filter. The Sallen-Key filter can be used

for this task, as Figure 40 shows. For best results, the amplifier must have a bandwidth that is 8 to 10 times the

filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.

Figure 40. Two-Pole, Low-Pass, Sallen-Key Filter

l TEXAS INSTRUMENTS I \ Vuuh : Vm

out inV V

2.7V

Vout+

Vout-

V+

Vdiff

Vref

2.5V

Vin

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

8.2 Typical Application

Some applications require differential signals. Figure 41 shows a simple circuit to convert a single-ended input of

0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited

to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a

voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–.

VOUT+ and VOUT– range from 0.1 V to 2.4 V. The difference, VDIFF, is the difference between VOUT+ and

VOUT– which makes the differential output voltage range 2.3 V.

Figure 41. Schematic for a Single-Ended Input to Differential Output Conversion

8.2.1 Design Requirements

Table 1 lists the design requirements:

Table 1. Design Parameters

DESIGN PARAMETER VALUE

Supply voltage 2.7 V

Reference voltage 2.5 V

Input voltage 0.1 V to 2.4 V

Output differential voltage ±2.3 V

Output common-mode voltage 1.25 V

Small-signal bandwidth 5 MHz

8.2.2 Detailed Design Procedure

The circuit in Figure 41 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and

VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a

buffered version of the input signal, VIN (as shown in Equation 1). VOUT– is the output of the second amplifier

which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for

VOUT– is given in Equation 2.

(1)

l TEXAS INSTRUMENTS V (7 Vd Vum- : Vm Vuul : Vver Vm Vdm = 2 x Vm , Vvel V +

out out

cm ref

V V 1

V V

2 2

 

§ ·

¨ ¸

diff in refV 2 V V u 

out ref inV V V 

out inV V

2 4 2

diff out out in ref

1 3 4 1

R R R

V V V V 1 V 1

R R R R

  § ·

§ · § ·

 u   u u 

¨ ¸

¨ ¸ ¨ ¸



4 2 2

out ref in

3 4 1 1

R R R

V V 1 V

R R R R

§ · § ·

u u   u

¨ ¸ ¨ ¸

© ¹

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

(2)

The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and

VOUT–. Equation 3 shows the transfer function for VDIFF. Using conditions in Equation 4 and Equation 5 and

applying the conditions that R1= R2and R3= R4, the transfer function is simplified into Equation 6. Using this

configuration, the maximum input signal is equal to the reference voltage, and the maximum output of each

amplifier is equal to VREF. The differential output range is 2 × VREF. Furthermore, the common-mode voltage is

one half of VREF, as shown in Equation 7.

(3)

(4)

(5)

(6)

(7)

8.2.2.1 Amplifier Selection

Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing

limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.

Bandwidth is a key concern for this design, so the OPAx316 is selected because the bandwidth is greater than

the target of 5 MHz. The bandwidth and power ratio makes this device power efficient and the low offset and drift

ensure good accuracy for moderate precision applications.

8.2.2.2 Passive Component Selection

Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low

tolerances to maximize performance and minimize error. This design uses resistors with resistance values of

49.9 kΩand tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance

values (6 kΩor lower) can be selected to keep the overall system noise low. This ensures that the noise from the

resistors is lower than the amplifier noise.

l TEXAS INSTRUMENTS

-2.50

-2.00

-1.50

-1.00

-0.50

0.00

0.50

1.00

1.50

2.00

2.50

0.00 0.50 1.00 1.50 2.00 2.50

Vdiff (V)

Input voltage (V)

C027

0.00

0.50

1.00

1.50

2.00

2.50

0.00 0.50 1.00 1.50 2.00 2.50

Vout+ (V)

Input voltage (V)

C027

0.00

0.50

1.00

1.50

2.00

2.50

0.00 0.50 1.00 1.50 2.00 2.50

Vout- (V)

Input voltage (V)

C027

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

8.2.3 Application Curves

The measured transfer functions in Figure 42,Figure 43, and Figure 44 are generated by sweeping the input

voltage from 0.1 V to 2.4 V. The full input range is actually 0 V to 2.5 V, but is restricted by 0.1 V to maintain

optimal linearity. For more details on this design and other alternative devices that can be used in place of the

OPAx316, see (Single-Ended Input to Differential Output Conversion Circuit Reference Design (TIPD131).

Figure 42. VOUT+ vs Input Voltage Figure 43. VOUT– vs Input Voltage

Figure 44. VDIFF vs Input Voltage

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

9 Power Supply Recommendations

The OPAx316 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from

–40°C to +125°C. Typical Characteristics presents parameters that can exhibit significant variance with regard to

operating voltage or temperature.

CAUTION

Supply voltages larger than 7 V can permanently damage the device (see the Absolute

Maximum Ratings) table.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more information on bypass capacitor placement, see Layout Guidelines.

l TEXAS INSTRUMENTS

N/C

±IN

+IN

V±

V+

OUTPUT

N/C

VS+

GND

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Use low-ESR, ceramic

bypass capacitor

Place components

close to device and to

each other to reduce

parasitic errors

Use low-ESR,

ceramic bypass

capacitor

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the

operational amplifier. Bypass capacitors reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most

effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to

ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to

physically separate digital and analog grounds, paying attention to the flow of the ground current. For

more detailed information, see Circuit Board Layout Techniques (SLOA089).

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much

better than crossing in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the

inverting input minimizes parasitic capacitance, as shown in Layout Example .

• Keep the length of input traces as short as possible. Remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

Figure 45. Operational Amplifier Board Layout for Noninverting Configuration

l TEXAS INSTRUMENTS Am

OPA316

OPA2316

OPA2316S

OPA4316

www.ti.com

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

•EMI Rejection Ratio of Operational Amplifiers (SBOA128).

•QFN/SON PCB Attachment (SLUA271).

•Quad Flatpack No-Lead Logic Packages (SCBA017).

•Single-Ended Input to Differential Output Conversion Circuit Reference Design (TIPD131).

•Circuit Board Layout Techniques (SLOA089).

11.2 Related Links

The following table lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

OPA316 Click here Click here Click here Click here Click here

OPA2316 Click here Click here Click here Click here Click here

OPA2316S Click here Click here Click here Click here Click here

OPA4316 Click here Click here Click here Click here Click here

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

l TEXAS INSTRUMENTS

OPA316

OPA2316

OPA2316S

OPA4316

SBOS703F –APRIL 2014–REVISED OCTOBER 2016

www.ti.com

Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

OPA2316ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2316

OPA2316IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OVMQ

OPA2316IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OVMQ

OPA2316IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2316

OPA2316IDRGR ACTIVE SON DRG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SMD

OPA2316IDRGT ACTIVE SON DRG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SMD

OPA2316SIDGS ACTIVE VSSOP DGS 10 80 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 SMG

OPA2316SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 SMG

OPA2316SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1QU

OPA2316SIRUGT ACTIVE X2QFN RUG 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1QU

OPA316IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SLE

OPA316IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SLE

OPA316IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SLD

OPA316IDCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SLD

OPA4316ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O4316D

OPA4316IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O4316D

OPA4316IPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4316

OPA4316IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4316

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2316, OPA316, OPA4316 :

•Automotive: OPA2316-Q1, OPA316-Q1, OPA4316-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS 5:. V.’

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

OPA2316IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2316IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA2316IDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

OPA2316IDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

OPA2316SIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2316SIRUGR X2QFN RUG 10 3000 180.0 8.4 1.75 2.25 0.55 4.0 8.0 Q1

OPA2316SIRUGT X2QFN RUG 10 250 180.0 8.4 1.75 2.25 0.55 4.0 8.0 Q1

OPA316IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3

OPA316IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

OPA316IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

OPA316IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

OPA4316IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

OPA4316IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA2316IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0

OPA2316IDR SOIC D 8 2500 356.0 356.0 35.0

OPA2316IDRGR SON DRG 8 3000 367.0 367.0 35.0

OPA2316IDRGT SON DRG 8 250 182.0 182.0 20.0

OPA2316SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0

OPA2316SIRUGR X2QFN RUG 10 3000 210.0 185.0 35.0

OPA2316SIRUGT X2QFN RUG 10 250 210.0 185.0 35.0

OPA316IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0

OPA316IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0

OPA316IDCKR SC70 DCK 5 3000 180.0 180.0 18.0

OPA316IDCKT SC70 DCK 5 250 180.0 180.0 18.0

OPA4316IDR SOIC D 14 2500 340.5 336.1 32.0

OPA4316IPWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

OPA2316ID D SOIC 8 75 506.6 8 3940 4.32

OPA2316IDGK DGK VSSOP 8 80 330 6.55 500 2.88

OPA2316SIDGS DGS VSSOP 10 80 330 6.55 500 2.88

OPA4316ID D SOIC 14 50 507 8 3940 4.32

OPA4316IPW PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/F 06/2021

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

DGSOO10A I

www.ti.com

PACKAGE OUTLINE

TYP

5.05

4.75

1.1 MAX

8X 0.5

10X 0.27

0.17

0.15

0.05

TYP

0.23

0.13

0 - 8

0.25

GAGE PLANE

0.7

0.4

NOTE 3

3.1

2.9

NOTE 4

3.1

2.9

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

110

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 3.200

DGSOO10A

www.ti.com

EXAMPLE BOARD LAYOUT

(4.4)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

10X (1.45)

10X (0.3)

8X (0.5)

(R )

TYP

0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

DGSOO10A

www.ti.com

EXAMPLE STENCIL DESIGN

(4.4)

8X (0.5)

10X (0.3)

10X (1.45)

(R ) TYP0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam AB, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddiﬁ§n%="" 5.40="" 5,40="" @eeeeeej="" rﬁhﬂ§eﬂhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com

MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end ﬂair \Meﬁead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com

PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Deﬁned Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">

MECHANICAL DATA RX)”; 1111141137121 :11? D1 /'\i3T1C QUAD F1 A’lWCK 11:7 777775 1 v 1 7 3 1 A V A V p a 1 1 2 3 a 1 1 1 1 A 1 1 ‘ 1 + 7 + V 1 v } +7 1 A 7 ‘ 7 7 1 F 1 9 s 7 a 1 . ‘ 1 > 4 420852873/5 04/2008 N0 {5* camp A11 11necr mmensmrs Ne m m 11metef§ 111s drawmq 1s sumo 0 change 111110 0:11 (am mum NaiLeud) pm W15 package comphes kc VEDEC MO 288 v: D1mensonmq and m1erc'1c1ng per ASM; V14 2111171954 nohcc uvctmnv ahun XZEFD INSI'RUMENTS www.1i.com

LAND PATTERN [Xumpe Boara Layout txomte stem Design (Note E‘, fit rimmtmﬂex WEBER ‘E gm‘wtm ~ Jam; II at « NOTES, A AH \wec' dtmenstons we try mrt‘rmezers B ttrs drawmq rs east :0 chanqn wrtrraa: metres 0 Pubhcutton PC 735' ts recarrmencea tar atterrate aestqns 3 Cusiomevs stauta w'vtuct ttre‘rr boc'd -'a can s'rte '0' rrr'rrrrram sataer musk web (oe'ances betwee'v st'qnc pads ’ \Acxtmum sterert tmmess om mrr (5 ms) AH trnear dtmens'ms are In rmurmeters F Laser eattma apertures wth :raaezaraat wcHs ara usu roundtng comers wru atter aetter paste retease Cusicmers mate Coniuct mew beard aesematy s'te (0' sterrert destqv recomme 'vs Reter ta PC 7525 rar stenc‘ aes' aarrsraeratrans c Stde uperU'e d'me'vstuns overiprmt mm ‘or cccepmhe area r o > use Cusiomer rruy 'educe sae aperture atmens‘raes 'i szene't manduciurmg a'ocess uHows tar sattreren: retease at smater upemng. #3 ”Dams [usmmms www.!i.com

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud ﬂasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com

LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Deﬁned Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH oﬂer eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com

MECHANICAL DATA DLHST‘ 3 SM ALL OU’ \j Q, [AC mam/c wz/m AH Mnec' dwmenswors c'e m m hmeters Dwmenswmmg one «meranmg per ASME vaAeaL Th5 dvuwmg 1: sub 0 change mum: "om SON {31'qu Cuihne Nomad) suckuge cmvhgmuhon. We pacmge We’ma‘ pad mm be Jcered to (he boarc (or Warm: and mec'vumca‘ performance See me Pmdud Dam Sweet M de us veguvdmg the exposed Ovev'm pud mmensmns JEDEC M07229 Duckuge 'egistvutu'v pendmg. {if TEXAS INSTRUMENTS www.1i.com

--I

www.ti.com

PACKAGE OUTLINE

8X 0.3

0.2

2 0.1

1.5

1.2 0.1

6X 0.5

0.8

0.7

8X 0.6

0.4

0.05

0.00

A3.1

2.9 B

3.1

2.9

(0.2) TYP

WSON - 0.8 mm max heightDRG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218885/A 03/2020

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.08 C

THERMAL PAD

EXPOSED

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 5.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.25)

(2)

(2.7)

6X (0.5)

(1.2)

( 0.2) VIA

TYP

(0.75)

8X (0.7)

(R0.05) TYP (0.35)

WSON - 0.8 mm max heightDRG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218885/A 03/2020

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

8X (0.25)

8X (0.7)

(1.13)

(1.79)

(2.7)

6X (0.5)

WSON - 0.8 mm max heightDRG0008A

PLASTIC SMALL OUTLINE - NO LEAD

4218885/A 03/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

84% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

SYMM

METAL

TYP

SYMM

MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane ﬁt Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom ﬂcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com

LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencﬂ tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'ﬂe' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercﬂ des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncﬂ rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

OPA316, 2316(S), 4316 Datasheet by Texas Instruments

INFORMATION

HELP

CONTACT US

FOLLOW US