NCP5214 Datasheet by ON Semiconductor

2−in−1 Notebook DDR

The NCP5214 2−in−1 Notebook DDR Power Controller is

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SWDDQ M2

VDDQ 1.8 V, 10 A

1.8 mH

1 VDDQEN VDDQ regulator enable input. High to enable.

2 VTTEN VTT regulator enable input. High to enable.

3 FPWM Forced PWM enable input. Low to enable forced PWM mode and disable power−saving mode.

4 SS VDDQ Soft−start capacitor connection to ground.

5 VTTGND Power ground for the VTT regulator.

circuitry.

15 PGOOD Power good signal open−drain output.

16 OCDDQ Overcurrent sense and program input for the high−side FET of VDDQ regulator. Also the battery

voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input

voltage variation. This pin must be connected to the VIN through a resistor to perform the current limit

17 BOOST Positive supply input for high−side gate driver of VDDQ regulator and boost capacitor connection.

18 TGDDQ Gate driver output for VDDQ regulator high−side N−Channel power FET.

capacitor of the VDDQ regulator high−side gate driver supply.

0.3 (dc), 32 V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values

(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage

may occur and reliability may be affected.

2. Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78.

3. Pin 16 (OCDDQ) must be pulled high to VIN through a resistor.

TA = −40 to 85°C0.788

4. Guaranteed by design, not tested in production.

(Sink Current)

IVTTR = 0 mA to 15 mA

IVTTR = 0 mA to 15 mA

reaches the minimum frequency at about 15 kHz.

pin establishes a voltage drop across this resistor and

current and up to 2.4 A transient peak current. It is activated

ground of local VDDQ bypass capacitor for load.

and VTTGND pins. The FBVTT should be connected to

the VTT regulation point, which is usually the VTT local

should be connected via a direct sense trace to the ground

output voltage. The PGOOD is pulled low when the VDDQ

thold X 200 ms

VTTEN goes LOW

and to turn off VTT.

VIN goes above the

normal mode.

withstand the large current pulses present at the input of the

high voltage rating. POSCAP or OS−CON capacitors can

rating, but they are larger in size and more expensive.

X7R types are ceramic capacitors and have smaller

tolerance and temperature coefficient.

Output Capacitor Selection for VDDQ Buck Regulator

steady state output ripple voltage, load transient

large enough to meet the overshoot and undershoot during

load transient. Since steady state output ripple voltage,

capacitance of the output capacitor are the contributing

The output ripple voltage is calculated as follows:

where IL(ripple) is the inductor ripple current, ton is on−time,

output capacitor with smaller ESR. Thus, the ESR needed

to meet the ripple voltage requirement can be obtained by:

maximum load current and the ripple voltage is typically

simplified to:

both the load−rise and the load−release responses. The

by the equation:

term is ignored, then it becomes the following inequality:

from the above inequality.

(eq. 11)

where ISTEP(peak) is the load current step plus half of the

ripple current at the load release and DILOAD is the change

Inductor Selection

The inductor should be chosen according to the inductor

elements of the buck controller. Both high−side and

considered when choosing the MOSFETs.

5.0 mW can achieve good efficiency.

application.

time (150 ns) to avoid false current limit triggering. When

closed to the lead of the current limit setting resistor RL1

Compensation network DC Gain can be calculated by the

are defined by the below equations:

GAIN (dB)

Figure 40. Asymptotic Bode Plot of the Converter Gain

Since the ramp amplitude of the PWM modulator has a

Below are some guidelines for setting the compensation

1. Set a value for R1 between 2.0 kW and 5.0 kW.

2. Set a target for the close loop bandwidth which

(eq. 32)

Phase(Filter) +− tan −1(2pf ESR COUT)− tan −1ǒ2pf ESR )DCR COUT

The phase of the Type III compensation network can be calculated by:

The close loop phase can be calculated by summing the

Then the close loop phase margin can be estimated by:

Phase(Margin) +Phase(CloseLoop) *(*180°)

It should be checked that closed loop gain has a 0 dB gain

45° or greater. The compensation components values may

require some adjustment to meet these requirements.

error amplifier open loop gain to make sure that it is

contributed by R1. If the value of R1 is changed, the

and the system stability will be affected. Besides, it is

to prevent surge current from power supply and output

the soft−start voltage. When the soft−start voltage reaches

Ceramic capacitors with low tolerance and low

temperature coefficient, such as B, X5R, X7R ceramic

capacitors are recommended to be used as the CSS. Ceramic

Therefore, the VTT soft−start time tSSVTT can be estimated

boost voltage for the supply of the high−side gate driver of

the bulk regulator. Schottky diode with low forward

voltage and 0.5 A DC current ratings can be used as the

capacitor.

no bypass capacitor is required to add to VTTI since the

Besides, the maximum load current of VDDQ is the sum of

3. Static tolerance: 2% ("36 mV).